1. Field of the Invention
This invention relates generally to capacitors for semiconductor devices, and more particularly, to a method for forming a capacitor having a tantalum oxide dielectric using a two-step rapid thermal nitridation process.
2. Description of the Related Art
In general, each memory cell of a dynamic random access memory (DRAM) includes one capacitor and one transistor. Each capacitor, which is used for storing information, is very important for the DRAM device. However, as semiconductor devices becomes more highly integrated and device geometries become finer, each memory cell becomes smaller and lower operational voltages are used. Accordingly, it is necessary to increase the capacitance of each capacitor to obtain the desired drive characteristics for each cell. If the capacitance is insufficient, the refresh time is reduced, and the reliability and yield ratio thereof deteriorate. However, even though increased integration levels result in increased leakage current, acceptable devices are still obtained, and production efficiency increases, if the capacitance exceeds a predetermined level.
Some techniques for increasing the cell capacitance include: increasing the effective area of a capacitor by employing a cylindrical or pin-type storage electrode; forming a dielectric layer using a high dielectric material; and reducing the thickness of the dielectric layer. One method for forming a dielectric layer using a high dielectric material involves forming a Ta.sub.2 O.sub.5 dielectric layer having good step coverage even at the storage node of a complicated structure. Such a technique is disclosed in the paper "Ultrathin Tantalum Oxide Capacitor Dielectric Layer Fabricated Using Rapid Thermal Nitridation Prior To Low Pressure Chemical Vapor Deposition" by S. Kamiyama et al., Soc., Vol. 140, No. 6, P.1617, 1993, NEC Co.
FIG. 1 is a flowchart illustrating a conventional method for forming a capacitor having a Ta.sub.2 O.sub.5 dielectric layer. Referring to FIG. 1, a stack type storage node is formed on a semiconductor substrate where a lower structure is formed (step 51). Then a cleaning process is performed (step 53). Subsequently, a rapid thermal nitridation (RTN) process is performed in a NH.sub.3 atmosphere at 900.degree. C. for 90 seconds to form a nitride layer having a thickness of 7 .ANG. or more on the semiconductor substrate (step 55). A Ta.sub.2 O.sub.5 layer is deposited on the semiconductor substrate through low pressure chemical vapor deposition (LPCVD) where the RTN process has been performed (step 57), and then annealing is in a UV-ozone atmosphere (step 59). Then, wet or dry oxidation is performed for 30 min (step 61), and a barrier layer is deposited using TiN (step 63), Then a plate node is formed (step 65).
FIG. 2 is a graph of cell capacitance values measured after an RTN process is performed on a storage node having a surface with hemispherical grains (HSGs). Referring to FIG. 2, the X-axis indicates cell capacitance (fF/cell) and the Y-axis indicates the distribution (%) of measured points, respectively. The line represented by (.box-solid.) indicates the measured result after the RTN-process is performed at 900.degree. C. for 90 sec, and the line represented by (.quadrature.) indicates the measured result after the RTN-process is performed at 850.degree. C. for 90 sec. As shown in FIG. 2, the capacitance of a device processed at 850.degree. C. is larger than that at 900.degree. C. This is because the HSGs on the surface of the storage node are agglomerated through the RTN-process at 900.degree. C. That is, when the HSGs agglomerate, the effective surface area of the storage node is reduced, and thus the capacitance is reduced. Meanwhile, the HSGs processed at 850.degree. C. are less agglomerated than at 900.degree. C., and thus, their capacitance is greater. That is, when the RTN process is performed at 900.degree. C., the characteristics of the lower structure such as the storage electrode are deteriorated.
When the RTN is performed at 850.degree. C., the agglomeration of HSGs is suppressed, however, a thickness of the nitride layer produced therefrom is limited to a predetermined level.
FIG. 3 is a graph of the thickness of a nitride layer formed by performing an RTN-process at 850.degree. C. for various times. Referring to FIG. 3, the X-axis indicates RTN times and the Y-axis indicates the thicknesses of the resulting nitride layer. As shown in FIG. 3, when the RTN-process is performed at 850.degree. C., the nitride layer grows for approximately 100 sec, however, the nitride layer then arrives at a saturation state, and the growth of the nitride layer is suppressed at a thickness of less than 4.5 .ANG.. However, the thickness of a nitride layer formed through the RTN process should be at least 7 .ANG. to suppress oxidation of the storage node after deposition of the Ta.sub.2 O.sub.5 dielectric layer. When the RTN-process is performed at 850.degree. C., the thickness of the nitride layer is insufficient, and thus the nitride layer does not act as an oxidation barrier. Accordingly, during a later oxidation process, an oxide layer having a low dielectric constant is formed under the nitride layer. When the oxidation layer having a low dielectric constant grows under the nitride layer, the overall thickness of the dielectric layer increases, and thus, capacitance decreases and leakage current increases.
That is, when the RTN-process is performed at 900.degree. C., HSGs on the surface of the storage node agglomerate, thereby reducing the effective area of a capacitor and reducing the capacitance. Also, temperatures of 900.degree. C. or higher deteriorate the electrical characteristics of 256 megabit and 1 gigabit DRAM devices. However, when the RTN-process is performed at 850.degree. C., the HSGs on the surface of the storage node do not agglomerate, but the thickness of the nitride layer is limited to a predetermined level.